Memory is essential for a lot of things in your FPGA design. And FPGAs have a lot of different memory.
Content of this Episode:
* Flip-Flops
* SRAM blocks
* Ultra RAM
* Flash Memory
* High Bandwidth Memory
* Memory-Controller
* External Memory
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How can FPGAs calculate so fast? The secret inside an FPGA is a digital signal processing block.
Content of this Episode:
* What does DSP stand for?
* Common parts inside an DSP block
* Function representation
* Important facts
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We will dive deep into the FPGA architecture. This episode is about slices.
Content of this Episode:
* What are slices?
* Difference between FPGA manufacturer
* Configuration
* Housekeeping
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Have you ever asked yourself, what happens during FPGA implementation? In this episode I try to give an answer.
Content of this Episode:
* Placement
* Routing
* After routing process
* Similarity to a PCB layout
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Have you ever asked yourself, what happens during FPGA synthesis? In this episode I try to give an answer.
Content of this Episode:
* What is a netlist?
* Synthesis tool
* Elaboration Substep
* Matching to technology
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Let us talk about simulations and their benefits for your FPGA development projects.
Content of this Episode:
* Simulations in general
* Simulations in FPGA development
* Benefits for your FPGA development projects
* How to start with simulations
* What are the boundaries of simulation
* Simulate a hole design or only modules
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We are looking back on 2023 and then we try an outlook into 2024.
Content of this Episode:
* Happy New Year and all the best for 2024
* Review of 2023
* some private facts
* Business
* Outlook into 2024
* Business
* Private things
* Next webinar in February 2024
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In addition to the last episode we will now have a look into the process of debugging an ARM core software.
Content of this Episode:
* Debugging an ARM (in a SoC)
* Use UART and printf
* Debug your bare metal application in Vitis
* Debug your Linux application in Vitis
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Let’s dive deeper into the debugging stuff. There are different ways of debugging an FPGA and the logic inside.
Content of this Episode:
* Debugging an FPGA
* Observe signal outputs
* Bring some internal signals to outer world
* Using a debug core
* Special case for ILA
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To start up a Xilinx Zynq SoC many steps are required. To get an overview we will talk today about bootloader.
Content of this Episode
* Stage-0 Boot (also known as BootROM)
* First Stage Bootloader (FSBL)
* Second Stage Bootloader
* Linux Kernel
* Init
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