Have you ever asked yourself, what happens during FPGA synthesis? In this episode I try to give an answer.
Content of this Episode:
* What is a netlist?
* Synthesis tool
* Elaboration Substep
* Matching to technology
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FPGA development is a lot of fun. But also think about an appropriate development process.
Content of this Episode:
* Electronics development process
* Validation vs. Verification
* Difference to the FPGA development process
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VHDL Testbenches have many interesting features to simulate and test your VHDL module. Let’s have a look into these functions.
Content of this Episode:
* VHDL Testbenches
* Using data files
* Multiple modules
* Automatic tests
* More automation
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We are looking back on 2024 and then we try an outlook into 2025.
Content of this Episode:
* Welcome in 2024
* Welcome back in this podcast 🙂
* Review of 2024
* some private facts
* Business
* Outlook into 2025
* Business
* Private things
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Let us talk about simulations and their benefits for your FPGA development projects.
Content of this Episode:
* Simulations in general
* Simulations in FPGA development
* Benefits for your FPGA development projects
* How to start with simulations
* What are the boundaries of simulation
* Simulate a hole design or only modules
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We are looking back on 2023 and then we try an outlook into 2024.
Content of this Episode:
* Happy New Year and all the best for 2024
* Review of 2023
* some private facts
* Business
* Outlook into 2024
* Business
* Private things
* Next webinar in February 2024
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In addition to the last episode we will now have a look into the process of debugging an ARM core software.
Content of this Episode:
* Debugging an ARM (in a SoC)
* Use UART and printf
* Debug your bare metal application in Vitis
* Debug your Linux application in Vitis
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Let’s dive deeper into the debugging stuff. There are different ways of debugging an FPGA and the logic inside.
Content of this Episode:
* Debugging an FPGA
* Observe signal outputs
* Bring some internal signals to outer world
* Using a debug core
* Special case for ILA
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One big question is: How did the intelligence come into the FPGA? Therefore we discuss in today’s episode two programming languages.
Content of this Episode:
* Programming languages
* Verilog
* VHDL
* Graphic input
* HLS = High Level Synthesis
The World of FPGA is opening on the 14th of march.
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After the last basic episode we will dive deeper today and look into different specialties of FPGAs.
Content of this Episode
* Some specialties of FPGAs
* Clock generation
* SERDES
* MIPI
* Processors
* Partial Reconfiguration
The World of FPGA is opening on the 14th of march.
Follow us on LinkedIn to get all news and also come into our pre-opening newsletter.